Bruno W. Garlepp

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A 0.25m CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge(More)
DAC network and the equalizer network to resolve setup and A 24Gb/s transmitter with a digital linear equalizer is hold time violations. Equalizer clock distribution is in the implemented in 90nm CMOS technology. It supports 4form of a mesh. The clock to the pattern-generator block channel Analog Multi-Tone (AMT) transmission, where each branches off from(More)
High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval(More)
MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency(More)
A MEMS-based clock generator achieves sub-ps jitter in 0.18um CMOS. Key enabling techniques include a 48MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25MHz achieves an integrated phase jitter of(More)
A CDR architecture is presented in 0.25μm CMOS that leverages a fully integrated hybrid analog/digital loop-filter structure to achieve the desired jitter performance with low area and power consumption while also allowing multi-rate operation at 155, 622, 1250, and 2500Mb/s data rates. The overall CDR performance exceeds SONET requirements. The small(More)
In this paper, a new technique for characterization of digital-to-analog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs Least Square Estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and(More)