Bruno W. Garlepp

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—A 0.25-m CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge(More)
Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23ps but its aperture center is more sensitive to supply(More)
DAC network and the equalizer network to resolve setup and A 24Gb/s transmitter with a digital linear equalizer is hold time violations. Equalizer clock distribution is in the implemented in 90nm CMOS technology. It supports 4-form of a mesh. The clock to the pattern-generator block channel Analog Multi-Tone (AMT) transmission, where each branches off from(More)
—MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional -N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency(More)
In this paper, a new technique for characterization of digital-to-analog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs Least Square Estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and(More)
High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval(More)
A 1-10Gbps receiver analog front end in 0.13�m CMOS enables a SERDES cell for backplane serial communications using differential PAM2, PAM4, or PAM2 partial response signaling with adaptive equalization. Dynamic sampler swapping and various built-in diagnostic capabilities enable receiver calibration and self-characterization with accuracy of < 0.4% UI in(More)
Random jitter (RJ) is a significant noise component in PLL systems that use ring-based oscillators. In order to estimate RJ, accurate modeling of the VCO phase noise is essential. In this paper, the authors will present how the VCO phase noise they obtained from HSPICE RF and from the Impulse-Sensitivity Function (ISF) method compared to lab measurements,(More)