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A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2m Le CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power(More)
This paper describes a senior/graduate level course in hardware logic verification being offered by The Ohio State University in cooperation with IBM. The need for the course is established through the growing importance of logic verification to users of custom logic designs. We discuss the short-term and long-term goals for the course, and describe the(More)
  • Bruce Wile
  • IBM Journal of Research and Development
  • 1997
TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS processor for the IBM S/390@ Parallel Enterprise Server Generation 4 to assist in designer-level logic verification. The concept of surrounding the logic design (hereafter referred to simply as “logic”) under test with irritator behaviorals, a methodology developed and proven effective on(More)
In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis(More)
Verification of the S/390@’ Parallel Enterprise Server G4 processor and level 2 cache (L2) chips was performed using a different approach than previously. This paper describes the methods employed by our functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure(More)
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