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—A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box–Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e.,(More)
—An efficient implementation of Nakagami-m and Weibull variate generators on a single field-programmable gate array (FPGA) is presented. The hardware model first generates a correlated Rayleigh fading variate sequence and then transforms it into a sequence of Nakagami-m or Weibull fading variates. A biquad processor facilitates the compact implementation of(More)
The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional(More)
—Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates(More)
— A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically accurate fading variates, namely, shaping the flat spectrum of Gaussian variates using digital filters and sum-of-sinusoids (SOS) based methods. Efficient design and(More)
—We present an ultra-compact and fast hardware simulator for Rayleigh and Rician fading channels. To ensure numerical robustness and an efficient mapping onto hardware, the fading simulator uses the sum-of-sinusoids technique with N = 32 sinusoids added up to model each fading path. Fading samples are generated at a low rate and then are passed to an(More)
—We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver(More)