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Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs). While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them. In this(More)
Identifying the dominant inductance in power distribution network design for multi-layer printed circuit boards that use power net area fills is essential. The plane-Pair partial element equivalent circuit method is used herein to extract a lumped inductance suitable for a physics-based circuit model for power net area fills. The method is being applied for(More)
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