Brian Nissim

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A 5.9-to-8.0 GHz fractional-N digital PLL with TDC histogram calibration, reference doubler compensation and non-periodic DCO dithering is implemented in 55nm CMOS. With reference doubled from 40 MHz, the rms jitter integrated from 1kHz to 10MHz is 0.19ps or 0.4° for a 5825 MHz clock measured at TX output, and the in-band noise floor is −108(More)
Growing demand in the broadband wireless communication market has resulted in emerging standards such as IEEE 802.16e (mobile WiMAX), which enable high data-rate communication over wide area coverage. Seamless switching between WiMAX and WLAN is envisioned as a means to enable users to stay connected anywhere and anytime. A low-cost low-power(More)
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