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This paper describes an integrated architecture, compiler, runtime, and operating system solution to exploiting heterogeneous parallelism. The architecture is a pipelined multi-threaded multiprocessor, enabling the execution of very fine (multiple operations within an instruction) to very coarse (multiple jobs) parallel activities. The compiler and runtime(More)
The Tera MTA is a revolutionary commercial computer based on a multithreaded processor architecture. In contrast to many other parallel architectures, the Tera MTA can effectively use high amounts of parallelism on a single processor. By running multiple threads on a single processor, it can tolerate memory latency and to keep the processor saturated. If(More)
[LeB86] T. J. LeBlanc. Shared memory versus message passing in a tightly-coupled multipro-cessor: A case study. The directory-based cache coherence protocol for the DASH multiprocessor. A comparison of programming models for shared memory multiprocessors. A comment on a fast parallel algorithm for thinning digital patterns. [ML91a] Evangelos P. Markatos and(More)
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