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This paper describes an integrated architecture, compiler, runtime, and operating system solution to exploiting heterogeneous parallelism. The architecture is a pipelined multi-threaded multiprocessor, enabling the execution of very fine (multiple operations within an instruction) to very coarse (multiple jobs) parallel activities. The compiler and runtime(More)
Register allocation is a vital stage in compiler optimization. It greatly impacts the effectiveness of other compiler optimization techniques. Graph coloring is the commonly used mechanism for register allocation. Since graph coloring is an NP-complete problem, heuristics are needed to find a practical solution. Several heuristics are available that perform(More)
The Tera MTA is a revolutionary commercial computer based on a multithreaded processor architecture. In contrast to many other parallel architectures, the Tera MTA can effectively use high amounts of parallelism on a single processor. By running multiple threads on a single processor, it can tolerate memory latency and to keep the processor saturated. If(More)
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