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Achieving high instruction issue rates depends on the ability to dynamicatty predict branches. We compare two schemes for dynamic branch prediction: a separate branch target buffer and an instruction cache based branch target buffer. For instruction caches of 4KB and greater, instruction cache based branch prediction performance is a strong function of tine(More)
A simple modification to an operating system's page allocation algorithm can give physically addressed caches the speed of virtually addressed caches. Colored page allocation reduces the number of bits that need to be translated before cache access, allowing large low-associativity caches to be indexed before address translation, which reduces the latency(More)
Virtual memory requires address translation to map a virtual address to a physical address. To reduce the performance penalty of address translation, the most recent address translations are cached in a translation lookaside buffer (TLB). To access a medium to large low-associative cache with the physical address, the TLB access must precede the cache(More)
For high performance, data caches must have a low miss rate and provide high bandwidth, while maintaining low latency. Larger and more complex set associative caches provide lower miss rates but at the cost of increased latency. Interleaved data caches can improve the available bandwidth, but the improvement is limited by bank conflicts and increased(More)
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