Brian K. Bray

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Brian K. Bray and M. J. Flynn Computer Systems Laboratory Startford Urtiversity, CA 94305 Achieving high instruction issue rates depends on the ability to dynamicatty predict branches. We compare two schemes for dynamic branch prediction: a separate branch target buffer and an instruction cache based branch target buffer. For instruction caches of 4KB and(More)
Virtual memory requires address translation to map a virtual address to a physical address. To reduce the performance penalty of address translation, the most recent address translations are cached in a translation lookaside buffer (TLB). To access a medium to large low-associative cache with the physical address, the TLB access must precede the cache(More)
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