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– A CMOS voltage reference using compensation of mobility and threshold voltage temperature effects is proposed. In this reference, the nested connection of two NMOS transistors supplies a voltage with positive temperature coefficient, and the diode-connected NMOS transistor supplies a voltage with negative temperature coefficient. These two circuits are(More)
A non-contact method for parallel testing of System-in-Package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a(More)
A method for wireless, non-contact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card(More)
Non-contact methods for testing System-on-Chip (SoC) and System In Package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy-an issue(More)
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