Brandon Greenley

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A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 m 94 m die area. A segmented R-2R(More)
This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R(More)
A method for distributing capacitor and resistor area to optimally reduce die area in a given continuous-time filter design while maintaining the filter’s designed signal-to-noise ratio (SNR), frequency response, and topology is discussed. To do this, a basic linear programming algorithm is developed from derived circuit cost and constraint functions. Among(More)
would also like to thank my committee members for their valuable feedbacks. When I first start my study in the lab ECE245, there were numerous people who helped me. They include Hardy Schmidtbauer who were always good mentors to me. In particular, I would like to thank José Silva for helping me with valuable CAD support and Robert Batten for testing. It had(More)
0 . 1 8 ~ CMOS process. The DAC is optimized for circuit calibration in large ASICs and occupies 0.01034 mm’ (1 IOW x 9 4 ~ ) of die area. Creative layout and current mirroring techniques are implemented to minimize area while providing output current with sufficient headroom. The measured DNLfiNL is better than 0.7/0.75 LSB and OH2 LSB for 1.8V and 1.4V(More)
In this work a new voltage buffer, the drain-follower, achieves 300MHz bandwidth with 2pF load, a dc gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 1.4Vpp output voltage and 6.5mW power dissipation from 5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5μm CMOS technology. The circuit has(More)
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