Bradley S. Carlson

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A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic(More)
This paper explores parallel logic simulation on a network of workstations using a parallel virtual machine (PVM). A novel parallel implementation of the centralized-time event-driven logic simulation algorithm is carried out such that no global controlling workstation is needed to synchronize the advance of simulation time. Further advantages of our new(More)