Bradley F. Dutton

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This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under test, control of BIST execution, retrieval of BIST results, and fault diagnosis. The approach was implemented in Xilinx Virtex-5 FPGAs but is applicable to(More)
A design for the detection and correction of single event upsets (SEUs) in the configuration memory of field programmable gate arrays (FPGAs) is presented. Larger configuration memories and shrinking design rules have caused concerns to rise about SEUs in high-reliability high-availability systems using FPGAs. We describe the operation and architecture of(More)
—A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 and Virtex-5 Field Programmable Gate Arrays (FPGAs). The Frame ECC logic facilitates the detection of Single Event Upsets (SEUs) in the FPGA configuration memory. The ICAP provides(More)
—Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults(More)
This paper presents a software based approach for automatic generation of digital circuitry for synthesis and incorporation in a mixed-signal circuit or system to provide Built-In Self-Test (BIST) and measurement of the analog circuitry. The measurements supported by the BIST circuitry include frequency response (both gain and phase), linearity and noise(More)
Larger field programmable gate array (FPGA) configuration memories and shrinking design rules have raised concerns about single event upsets (SEUs), especially for high-reliability, high-availability systems that use FPGAs. We present a design for the on-line detection and correction of SEUs in the configuration memory of Xilinx Virtex-4 and Virtex-5 FPGAs.(More)
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