Bradley F. Dutton

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A Built-In Self-Test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults(More)
A design for the detection and correction of single event upsets (SEUs) in the configuration memory of field programmable gate arrays (FPGAs) is presented. Larger configuration memories and shrinking design rules have caused concerns to rise about SEUs in highreliability high-availability systems using FPGAs. We describe the operation and architecture of(More)
A Built-In Self-Test (BIST) approach is presented for the logic resources in the programmable input/output (I/O) tiles in Virtex-5 field programmable gate arrays (FPGAs). A total of 15 BIST configurations were developed to test the I/O cell programmable logic resources in all modes of operation. The approach utilizes dedicated I/O buffer bypass routing in(More)
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under test, control of BIST execution, retrieval of BIST results, and fault diagnosis. The approach was implemented in Xilinx Virtex-5 FPGAs but is applicable to(More)
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults in(More)
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 and Virtex-5 Field Programmable Gate Arrays (FPGAs). The Frame ECC logic facilitates the detection of Single Event Upsets (SEUs) in the FPGA configuration memory. The ICAP provides(More)
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that the user can be assured that their system function is downloaded to a fault-free device. In this paper, we present case studies of developing BIST configurations for some of the(More)