Boonchuay Supmonchai

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This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute transform of flexible input combinations. The architecture can support all transform sizes i.e. 4×4,(More)
A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six(More)
The design of a scalable optical local area network formultiprocessing systems is described. Each workstation has aparallel-fiber-ribbon optical link to a centralized complementarymetal-oxide silicon (CMOS) switch core, implemented on a singlecompact printed circuit board (PCB). When the Motorola Optobusfiber technology is used, each workstation has a data(More)
The design of a fiber-optic local area network (LAN) demonstration system is described. A complete LAN system would consist of an array of 16 personal computers (PC's), where each PC has a network interface card (NIC) with a parallel fiber-optic datalink to a centralized optoelectronic switch core. The centralized core switches the data generated by 16(More)
A tree multiplier design approach based on dual voltage supply technique is proposed. The design consists of two types of full-adder units, one with a higher voltage supply (3.3 V) and the other at lower voltage (2.5 V). The 3.3 V full-adder units are used exclusively in the most critical path of the multiplier to guarantee its best overall performance(More)
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