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SUMMARY This paper proposes two high-performance multi-threshold-voltage CMOS (MTCMOS) F/Fs that are based on the CMOS hybrid-latch F/F and the CMOS semi-dynamic F/F. The proposed F/Fs utilize a clock-gating technique or a data recovery circuit in order to preserve their logic states in the power-down mode. They can change operation modes whether the clock(More)
As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we analyze the effects of process variations on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte-Carlo based transistor-level simulations including principal(More)
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