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This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz - 2.5 GHz with channel bandwidths(More)
Classical analysis of transistor amplifier performance shows 9.6 dB as the difference between the input-referred third-order intercept point (IIP3) and 1-dB gain compression point. An analysis of amplifier gain compression shows that this is not the case, that at least fifth-order harmonics play a role in the gain compression curve and that the classical(More)
Dithering is used in many discrete to continuous value conversion functions to provide an effective fractional value. This paper reviews the application of dither to a digital-to-time converter (DTC) based digital synthesizer suitable for many common wireless communication systems. Measurements of a 90 nm CMOS implementation using a 5 bit DTC show extension(More)
This paper reports a flexible direct digital modulation based low power transmitter in 90 nm CMOS that supports constant-envelope modulation using phase or frequency modulation for carrier frequencies from 100 MHz to 2.5 GHz. For rectangular filtered 8-PSK modulation from 1 K symbol/s to 20 M symbol/s the RMS phase error is less than 4 deg. Frequency(More)
Providing all band power amplification and harmonic rejection are objectives with orthogonal implementations. This paper is a review of a new Distributed Power Amplifier (DPA) architecture using programmable frequency dispersion. This frequency domain dispersion is designed to achieve electronic harmonic filtering within the intended frequency band. Tunable(More)
Abstract—A fundamental requirement of an SDR transceiver is signal generation and processing across all frequencies of interest. Motorola's 90 nm SDR transceiver chip implementation has achieved continuous coverage from 0.1 4 GHz with the introduction of integrated direct digital synthesis (DDS). This is based on an innovative new architecture called(More)
High efficiency amplifier operation (class-D, E and S) conceptually approaches an ideal switched transistor model. Driver signals are of sufficient level to ensure that the devices are saturated and cut off during the proper parts of the RF cycle. Conventional sine wave input signals are generated with lower efficiency cascaded power gain stages. Deep(More)
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