Bo-Wei Hsieh

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Computational efficiency is one of the major challenges of applying simulation to short-term operation scheduling of semiconductor wafer fabrication factories (fabs), which are characterized by re-entrant process flows, stringent production control requirements and fast changing technology and business environments. This paper explores the application of(More)
Semiconductor wafer fab operations are characterized by complex and reentrant production processes over many heterogeneous machine groups with stringent performance requirements. Efficient composition of good scheduling policies from combinatorial options of wafer release and machine dispatching rules has posed a significant challenge to competitive fab(More)
In this paper, we exploit the speed of an ordinal optimization (OO)-based simulation tool designed by Hsieh et al. to investigate dynamic selection of scheduling rules for semiconductor wafer fabrication (fab). Although a scheduling rule is a combination of loading wafer release and dispatching rules, this paper specifically focuses on dispatching when(More)
A RF/Servo and backend Blu-ray player SoC providing 3D-rich playback is highly integrated on a 56.25mm<sup>2</sup> die in 55nm CMOS. Several cost-effective and high-throughput solutions are realized, leading to 3.85% and 23.13% of area and power reduction. This SoC includes 8&#x00D7; Read, 1080p at 30fps two-view decoding, stereo graphic and HDMI-1.4(More)
AbsiracfGExploiting the knowledge-based sofmare agent technology, this paper presents a design and its prototype implementation for learning agent-based semiconductor tool group dispatching. Core to the agent-based dispatching are decision and sequence tree-bused howledge representation models, the learning and acquisition mechanisms of dispatching policy(More)
DDR3 memory interface (I/F) with single-end signals is very sensitive to external environments, such as chip package type and system board design. In order to guarantee the system performance, IP providers often define the package and PCB design constraints to reduce product risks [1]. These design constraints may increase the package size and DDR3 PCB area(More)
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