Bjorn O. Bakka

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Two-level cache hierarchies will be a design issue in future high-performance CPUs. In this paper we evaluate various metrics for data cache<supscrpt>*</supscrpt> designs. We discuss both one- and two-level cache hierarchies. Our target is a new 100+ <italic>mips</italic> CPU, but the methods are applicable to any cache design. The basis of our work is a(More)
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