Bishwajeet Pandey

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In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40 nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes(More)
In this paper the effect of back off factor on exponential algorithm is analyzed and binary exponential algorithm is implemented in Mat lab. Binary Exponential Algorithm is widely used as a network congestion avoidance or collision resolution protocol. The detailed analysis of saturation throughput is done in this work. This work also covers packet's medium(More)
In this paper 64-bit energy efficient Arithmetic Logic Unit (ALU) is designed in verilog with the help of clock gating technique. We can reduce dynamic power and dynamic current of 64-bit ALU by using clock gating technique. This design is implemented on XC6VLX75T device, -3 speed grade and Virtex-6 FPGA. When clock logic is applied to target device, we are(More)
In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard(More)
In this work, we are going to use thermal aware approach in random access memory (RAM) design and also testing thermal stability by working on different ambient temperatures 285.15K, 288.15KC, 308.15C, 323.15K, 325.15K and 348.15K. We have observe the compatibility of our device with wireless network by working on different processor frequencies i.e. 1.2(More)
In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking(More)
In design and implementation of energy efficient register, we are using different I/O standard in 28nm Artix-7 FPGA, Verilog, Xilinx ISE 14.6 as simulator and XPower 14.6 as energy estimator and analyzer tool. This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O, HSTL(High Speed(More)
In this work, we designed a power efficient memory circuit using family of various HSTL IO Standards on 28nm Field Programmable Gate Array (FPGA). Nine different HSTL IO Standards are compared with each other to search the most power efficient one. We validated our circuit with different HSTL IO Standards and on Different frequency range to obtain a most(More)
In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three(More)