Bing-Chuan Bai

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Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are(More)
A two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that(More)
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