Bilge Saglam Akgul

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For scalable-shared memory multiprocessor System-on-a-Chip implementations, synchronization overhead may cause catastrophic stalls in the system. Efficient improvements in the synchronization overhead in terms of latency, memory bandwidth, delay and scalability of the system involve a solution in hardware rather than in software. This paper presents a(More)
To my mother, Mihrican Saglam, and my father, Mustafa Saglam, for their love, support and selfless sacrifices. iii ACKNOWLEDGMENTS I am grateful to everyone who made this Ph.D. thesis possible. First, I owe special thanks to my supervisor, Professor Vincent Mooney, for his patience and guidance from the very beginning until the end. Also, I would like thank(More)
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of lock latency, lock delay and memory bandwidth consumption in the system. It has been shown that a hardware solution brings a much better performance improvement than the(More)
Previous work has shown that a system-on-a-chip lock cache (SoCLC) reduces on-chip memory traffic, provides a fair and fast lock hand-off, simplifies software, increases the real-time predictability of the system and improves performance. In this research work, we extend the SoCLC mechanism with a priority inheritance support implemented in hardware.(More)
An effective and scalable synchronization mechanism is necessary for a heterogeneous multiprocessor shared-memory system-on-a-chip (SoC). A system-on-a-chip lock cache (SoCLC) is a simple hardware unit that can easily be integrated to an SoC as an intellectual property (IP) core via the system bus and has been shown to achieve speedups of 55% and 27% in(More)
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