Bhaskar Chatterjee

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This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in IOFF/mm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor IOFF reduction and ION degradation due to each technique(More)
In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in 3-5x increase in transistor I OFF /µm per generation resulting in 15%-30% noise margin degradation of high performance domino gates. We investigate several techniques that can improve the noise(More)
One of the challenging issues in optical networks is call blocking and it increases with the number of connection requests due to the limited number of wavelength channels in each fiber link. In this paper, we propose a priority based routing and wavelength assignment scheme with incorporation of a traffic grooming mechanism (PRWATG) to reduce call(More)
In this paper, we present simple analytical models for energy (switching + short circuit) per transition and delay for wide-NOR domino logic gates. These gates are used to design register files (RFs) in high performance microprocessors and priority encoders for content addressable memory (CAMs). They contribute significantly to the overall switching energy(More)
Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. This has resulted in the design of multi-gigahertz microprocessors with unprecedented levels of integration. However, this is posing serious challenges to IC testing and long-term reliability. A major source of failures and test escapes in high(More)
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the(More)
In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation(More)