Bharathwaj Raghunathan

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It is projected that increasing on-chip integration with technology scaling will lead to the so-called dark silicon era in which more transistors are available on a chip than can be simultaneously powered on. It is conventionally assumed that the dark silicon will be provisioned with heterogeneous resources, for example dedicated hardware accelerators. In(More)
In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with, such that the area and power budgets are met and the application performance is maximized. We(More)
In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with, such that the area and power budgets are met and the application performance is maximized. We(More)
The rate at which jobs arrive for processing at servers in a data-center (i.e., the job arrival rate) can vary significantly with time. Each server in a data-center is a multi-core processor, allowing jobs to be processed with different degrees of parallelism (DoPs) (i.e., number of threads per job). In this paper, we show both analytically and empirically(More)
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