Bernd Wuppermann

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To avoid SNR degradation due to jitter, sampling time errors must be less than 90fs rms. This accuracy is achieved through a combination of a low noise clock path and a 2-rank T/H architecture, as shown in Fig. 26.3.1. Clocked at the full 2.5GHz sampling rate via a low-jitter CMOS driver chain, the first T/H stage sets the sampling instant. Eight(More)
A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fsrms when N=2 and 206.1 fsrms when N=16. In addition, the PLL achieves loop bandwidths up to 100 MHz which enables it to be used as a clean-up PLL at the receiver. In(More)
We analyze computer-generated holograms (CGH) of Lohmann types I and III and discuss their overall errors employing the following modifications, listed in order of increasing importance: phase-only correction (Ptype), virtual increase of the cell number, optimized use of the available plotting area, expansion of the amplitude dynamic range (D-type),(More)
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