Learn More
Metastable events in ADC comparators cause large errors that cannot be tolerated in test and measurement applications that record data over extended time intervals. This work utilizes BiCMOS technology to provide high dynamic range analog to digital conversion at 2.5GS/s with a metastable error rate of less than one error per year and better than 78dB SFDR(More)
A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fsrms when N=2 and 206.1 fsrms when N=16. In addition, the PLL achieves loop bandwidths up to 100 MHz which enables it to be used as a clean-up PLL at the receiver. In(More)
  • 1