Berkehan Ciftcioglu

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— We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18m(More)
— Injection-locked clocking (ILC) has been proposed [1] to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then(More)
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The(More)
[11] A. Stroele, " BIST patter generators using addition and subtraction operations , " J. A concurrent built-in self-test architecture based on a self-testing RAM, " IEEE Trans. An on-chip march pattern generator for testing embedded memory cores, " IEEE Trans. Diagnostic data compression techniques for embedded memories with built-in self-test, " J.(More)
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