Benoit Provost

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This paper describes a new miniaturized implantable bladder controller that is composed of 4 main parts: a volume monitoring device based on the tomography approach, a fully programmable miniaturized central processor and stimulator, a bidirectional data and power link, and an external controller. The proposed system is intended to restore both normal(More)
A new implantable bladder volume-monitoring device based on the impedance measurement of the detrusor muscle is described. The system is completely autonomous and forms a mixed-signal (analogue/digital) feedback loop with a neuro-stimulator to rectify bladder dysfunctions (incontinence and retention) through neuromuscular stimulation techniques. A(More)
An efficient pipeline analog-to-digital converter (ADC) self-calibration implementation is presented. The technique uses a highly linear on-chip analog ramp generator, performs a simplified on-chip integral nonlinearity (INL) measurement, and extracts the compensation coefficients. Except for the ramp generator, the whole calibration is performed in the(More)
This paper presents the next generation AC IO Loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed(More)
Data eye margin test used in conjunction with loopback configuration has become a popular Design for Test (DFT) based test method for high speed links. This paper summarizes the DFT circuitry and test methods for supporting high speed serial interfaces (e.g. S-ATA,). The challenges of no-touch test methods in an external loopback environment are discussed.(More)
Being able to fully test a circuit is an important issue for quality manufacturing. Unlike fault analysis for digital circuits, analog fault analysis has been comparatively slow to evolve. The purpose of this paper is to study the feasibility of the time domain response analysis as a test method for analog circuits. The approach was to first study the fault(More)
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