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The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on-chip (SoC) and chip multiprocessors (CMP). In future high-performance CMPs, however, the high bandwidth requirements will not be adequately provided by electronic NoCs without(More)
As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that these gains are not nullified by high energy consumption from inter-core communication. With recent advances in 3D Integration CMOS technology, the possibility for realizing hybrid photonic-electronic networks-on-chip warrants investigating(More)
—Simultaneous all-optical switching of 20 continuous-wave wavelength channels is achieved in a microring resonator-based silicon broadband 1 2 2 comb switch. Moreover, single-channel power penalty measurements are performed during active operation of the switch at both the through and the drop output ports. A statistical characterization of the drop-port(More)
We demonstrate for the first time wavelength multicasting performed in a silicon photonic chip. We investigate multicast number selectivity at 40-Gb/s data rates and evaluate each configuration using BER measurements, establishing immense prospect for scalability. 1. Introduction Silicon has enjoyed a long-standing dominant role within the integrated(More)
As multicore architectures prevail in modern high-performance processor chip design, the communications bottleneck has begun to penetrate on-chip interconnects. With vastly growing numbers of cores and on-chip computation , a high-bandwidth, low-latency, and, perhaps most importantly , low-power communication infrastructure is critically required for next(More)
—An investigation of signal integrity in silicon pho-tonic nanowire waveguides is performed for wavelength-division-multiplexed optical signals. First, we demonstrate the feasibility of ultrahigh-bandwidth integrated photonic networks by transmitting a 1.28-Tb/s data stream (32 wavelengths 40-Gb/s) through a 5-cm-long silicon wire. Next, the crosstalk(More)
—A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband(More)
We demonstrate here a spatially non-blocking optical 4x4 router with a footprint of 0.07 mm 2 for use in future integrated photonic interconnection networks. The device is dynamically switched using thermo-optically tuned silicon microring resonators with a wavelength shift to power ratio of 0.25nm/mW. The design can route four optical inputs to four(More)
—The stringent on-and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an(More)