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Answer Set Programming (ASP) features effective optimization capacities based on branch-and-bound algorithms. Unlike this, in the area of Satisfiability Testing (SAT) the finding of minimum unsatisfiable cores was put forward as an alternative approach to solving Maximum Satisfiability (MaxSAT) problems. We explore this alternative approach to optimization(More)
Recently, Boolean Satisfiability (SAT) solving has been proposed to tackle the increasing complexity in high-level system design. Working well for system specifications with a limited amount of routing options, they tend to fail for densely connected computing platforms. This paper proposes an automated system design approach employing Answer Set(More)
We propose an SMT-based system synthesis approach where the logic solver performs static binding and routing while the background theory solver computes global time-triggered schedules. In contrast to previous work, we assign additional time to the logic solver in order to refine the binding and routing such that the background theory solver is more likely(More)
Networks on a Chip (NoCs) have been proposed to solve the communication challenges in Multi-Processor Systems on a Chip (MPSoCs) with ever increasing number of processing cores. They provide high bandwidth in combination with high connectivity, which is especially interesting in 3D integrated systems. However, efficiently exploiting both, processors and(More)
Precise knowledge of the longest sensitizable paths in a circuit is crucial for various tasks in computer-aided design, including timing analysis, performance optimization, delay testing, and speed binning. As delays in today's nanoscale technologies are increasingly affected by statistical parameter variations, there is significant interest in obtaining(More)
In hard real-time systems, where system complexity meets stringent timing constraints, the task of system-level synthesis has become more and more challenging. As a remedy, we introduce an SMT-based system synthesis approach where the Boolean solver determines a static binding of computational tasks to computing resources and a routing of messages over the(More)
The exploitation of the rapid growing field of Multiprocessor on chip requires efficient design methodologies and tools. Besides the extraction of task level parallelism, architecture synthesis is of growing importance, in particular for programmable hardware devices, which allow for the reuse of the hardware across applications. Using programmable devices(More)