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In this work, a simple assembled structure was designed and fabricated so that the calibration procedures on piezoresisitve stress sensors for microelectronic packaging can be simpler, more accurate, and more efficient. After comparing with the previous work results, validity of the aforementioned new structure was next demonstrated through experimental(More)
Moisture is one of the major contributing factors in fracture and reliability issues for microelectronic packaging. To characterize the moisture-induced stress distribution inside the packaging structure, an <i>in situ</i>, quantitative, and nondestructive experimental methodology is needed. This paper proposes the use of piezoresistive sensors to measure(More)
Because of the coefficient of thermal expansion and the hygroscopic swelling mismatches on plastic packaging materials, stress and reliability issues on microelectronic packaging structures are extremely important for the packaging industry. Through the self-design test chips with the piezoresistive microstress sensors, this paper presents the experimental(More)
The through silicon via (TSV) technology brings a key to 3D integration on wafer level packaging (WLP) by stacking chips to generate direct electrical interconnecting paths. Most of the related literatures employed the daisy chain test patterns to measure the electrical continuity and to evaluate the single via resistance. However, the single via resistance(More)
With the assistances from iteration methodology for heat dissipation property analyses and the effective material properties for the relatively complex PCB structures, this paper extracts the thermal resistance and the transient thermo-mechanical behaviors during reflow for two compactable high power diode packaging through the ANSYS software. After the(More)
In order to assess the reliability behavior of a typical TSV structure, this study describes the reliability tests to qualify the samples with three types of the TSV test-keys, which includes the Kelvin structure, the via-chain, and the meander metal lines. With enough number of the samples for statistic analyses, resistances of the samples were first found(More)
Stress measurements in microelectronic packaging through the MOSFET devices have attracted great attentions because the measurement is in-situ and nondestructive. In this study, a new assembled methodology was designed and applied so that the calibration procedures on MOSFET stress sensors can be simpler and more accurate. Under mechanical, thermal, and(More)
Three-dimensional (3D) structure with through silicon via (TSV) technology is emerging as a key issue in microelectronic packaging industry, and electrical reliability has become one of the main technical subjects for the TSV designs. However, criteria used for TSV reliability tests have not been consistent in the literature, so that the criterion itself(More)
TSV (Through Silicon Via) technology has been employed on packaging for CIS (CMOS Image Sensor) chips for many years. To assess the reliability behavior of a typical TSV design for CIS chips, the temperature humidity cycling tests (THCT) have been performed on self designed TSV samples but without current bias. Since the current bias lead electromigration(More)
As high performance MEMS devices are introducing, MEMS packaging using 3D high density packaging with Through Silicon Vias (TSV) technology becomes attractive. However, different criterions for reliability tests on TSV structures were found without consistency in the literature so that a study on criterion itself becomes necessary. To this end, this paper(More)