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Journals and Conferences
— This paper describes the issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers and proposes circuit techniques that can alleviate the drawbacks of this architecture. Following a brief study of hetero-dyne and image-reject topologies, the direct-conversion architecture is introduced and effects such as dc offset,… (More)
—The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-m CMOS technology, the receiver front-end provides a… (More)
— This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency… (More)
—Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite os-cillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators… (More)
—A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV pp for a bit-error rate of 10 12 while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while… (More)
— A dual-band receiver employs the Weaver architecture with two tuned radio-frequency stages and a common intermediate-frequency stage to allow operation with 900-MHz and 1.8-GHz standards while using only two oscillators. Fabricated in a digital 0.6-m CMOS technology, the receiver achieves an overall noise figure of 4.7 dB and input third intercept point… (More)
—A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-m CMOS technology in an area of 1 1 0 9 mm 2 , the circuit… (More)
—Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10… (More)
—A triple-resonance network increases the band-width of cascaded differential pairs by a factor of 2 3, yielding a 40-Gb/s CMOS amplifier with a gain of 15 dB and a power dissi-pation of 190 mW from a 2.2-V supply. An ESD protection circuit employs negative capacitance along with T-coils and pn junctions to operate at 40 Gb/s while tolerating 700–800 V.
—A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.