Learn More
— This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency(More)
—The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-m CMOS technology, the receiver front-end provides a(More)
— This paper describes the issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers and proposes circuit techniques that can alleviate the drawbacks of this architecture. Following a brief study of hetero-dyne and image-reject topologies, the direct-conversion architecture is introduced and effects such as dc offset,(More)
—A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-m CMOS technology in an area of 1 1 0 9 mm 2 , the circuit(More)