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—This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax(More)
The 2009 pandemic H1N1 influenza pandemic demonstrated the global health threat of reassortant influenza strains. Herein, we report a detailed analysis of plasmablast and monoclonal antibody responses induced by pandemic H1N1 infection in humans. Unlike antibodies elicited by annual influenza vaccinations, most neutralizing antibodies induced by pandemic(More)
—Fundamental oscillators prove the existence of gain at high frequencies, revealing the speed limitations of other circuits in a given technology. This paper presents an oscillator topology that employs feedback from an output stage to the core, thus achieving a high speed. The behavior of the proposed oscillator is formulated and simulations are used to(More)
A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step. This paper describes a pipelined ADC(More)
The RF design paradigm will change significantly as CMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This paper describes technology scaling issues such as low supply voltages, high gate leakage currents, and low transistor output impedances. Also, design techniques for(More)
—The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling methodology and a new half-rate speculative architecture for decision-feedback equalizers (DFEs) to relax the speed-power trade-offs. Designed in 90-nm CMOS technology, a 20-Gb/s prototype consisting of(More)