Behrad Niazmand

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Network-on-Chip (NoC) has been introduced as a novel solution to overcome the constraints met in on-chip interconnection networks. Performance of NoCs is one of the important concerns of researchers and designers. One of the factors that can affect performance in on-chip networks is the occurrence of congestion when routing packets. In this paper we(More)
Photonic-Network-on-chip (PNoC) has been proposed as a promising solution for the communication infrastructure of Chip Multiprocessors (CMPs) and as a solution to overcome the constraints in traditional NoCs. Photonic NoCs provide the opportunity of increasing both the bandwidth and the number of cores significantly, and can improve performance and the cost(More)
The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual(More)
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage(More)
The paper introduces automated minimization of a set of concurrent online checkers for Network-on-Chips (NoCs) under given fault detection quality constraints. The proposed framework allows accurate and complete evaluation of the fault detection capabilities of checkers, which in turn enables finding seamless trade-offs between the overhead area of the(More)
In this paper we describe a holistic approach for Fault-Tolerant Network-on-Chip (NoC) based many-core systems that incorporates a System Health Monitoring Unit (SHMU) which collects all the fault information from the system, classifies them and provides different solutions for different fault classes. A Mapper/Scheduler Unit (MSU) is used for online(More)
The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores increases, current electrical communication means can introduce serious challenges in system performance due to the restrictions in power consumption and communication bandwidth. Contemporary progresses in(More)
The deployment of mixed-criticality applications on NoC (Network-on-Chip)-based MPSoC (Multiprocessor System-on-Chip) platforms requires a stringent protection of the communication and processing resources being utilized by hard-real-time parts of the the application in order to avoid interference of less critical application parts. In this contribution we(More)
In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems is introduced. This system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework supports(More)
This paper proposes a framework for automated evaluation of concurrent online checkers. The novelty of the underlying approach lies in its completeness (i.e. ability of formally proving the presence or absence of true misses), minimal fault detection latency and accurate, fully automated evaluation of the fault detection characteristics of the checkers. The(More)