Basab Chatterjee

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The linear analysis of digital phase locked loop (DPLL) does not include finite precision arising owing to the limited size of register or memory for processing or storing the coefficients or data in most of the literatures. This truncation in word length results a serious degradation in DPLL performance. This paper addresses a problem where a truncation(More)
Analysis of BPSK homodyne receivers based on modified dither optical phase-locked loop, " Optik-Int. Optical microwave generation using modified sideband injection synchronization with wide line-width lasers for broadband communications, " Optik-Int. Analysis of BPSK homodyne receivers based on modified balanced optical phase-locked loop in the presence of(More)
A new second order digital phase locked loop is proposed with an acquisition aid from a fuzzy logic controller. Here, control signal of Digitally Controlled Oscillator (DCO) is adjusted by loop filter in addition with a fuzzy logic controller which uses carrier phase and frequency error as input data. This addition helps the loop to perform exceptionally(More)
A Fuzzy logic controller is employed here for controlling a 1st order digital phase locked loop (DPLL) based on adaptive loop gain criterion. This intelligent loop is changing its loop gain to vary the loop bandwidth for providing rapid and accurate control of DPLL in the transient and steady states. This form of Fuzzy DPLL is further modified by the(More)
An approach is introduced in this paper where a Fuzzy logic controller is incorporated in a conventional 2nd order digital phase locked loop (DPLL). Here, one of the loop filter coefficients is controlled by Fuzzy logic controller. This form of Fuzzy DPLL is further modified by inclusion of an additional phase control in the digitally controlled oscillator(More)
This paper puts forward a novel hierarchical approach for solving the problem of resistance extraction and current density profiling of lateral power MOSFETs mainly used in switching voltage regulators. In the absence of standard resistance extraction tools the design of such power arrays become quite difficult and iterative. The proposed algorithm exploits(More)
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