Balaji Vaidyanathan

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Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we(More)
Chip multiprocessors are becoming increasingly popular in embedded domain since they have important advantages over their single core counterparts from the parallelism, power efficiency, validation, and verification perspectives. However, extracting maximum performance from these multiprocessors requires compiler support in form of effective code(More)
Code compression techniques have been proposed to mitigate the problem of limited memory resources in embedded systems. As technology scales, reducing on-chip bus energy consumption is becoming important for embedded system designers. In this paper, we propose a crosstalk-aware energy-efficient code compression scheme, which can reduce inter-wire coupling(More)
Random process variation and variability intrinsic to PMOS Negative Bias Temperature Instability (NBTI-induced statistical variation) are two major reliability concerns as transistor dimensions scales with technology. Previous works have studied these two sources of variation separately at device and circuit level. We study the impact of the interaction(More)
Increasing use of on-chip networks as communication infrastructure in both high performance and low end computing makes it important to consider their power consumption. Several previously proposed approaches to power management in the context of NoCs (network-on-chips) are either pure hardware based or focus exclusively on a single application execution(More)
Control circuit in an asynchronous design is comprised mostly of Muller C-elements. Previous work has concentrated on power, performance, and area issues of various CMOS implementations of the C-element. In this paper we carried out a thorough soft error analysis of four popular CMOS implementations of the Muller C-element. It shows that SIL implementation(More)
On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associated with it and is estimated to increase with technology scaling. A recent work has proposed a gated decap structure to reduce leakage in decaps. Their work analyzes leakage saving(More)
Recent development in through-silicon via (TSV) technology has made multi-layer stacking (or 3D integration) a viable solution, opening possibility for coping with the issues related to poor interconnect scaling trend. In this direction, more uniform fabric like memories has been currently explored for benefits in 3D integration. There have been research(More)
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