Balaji Narasimham

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Four different latch designs are evaluated using heavy ion exposure and simulations. The latches were designed using the Transition AND Gate (TAG) in TSMC 0.35 mum technology. TAG based designs were(More)
In this paper, heavy-ion-induced single-event transient (SET) pulsewidths measured in a 65-nm bulk CMOS technology at temperatures ranging from 25°C to 100°C with an autonomous SET(More)