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A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects
As the chip multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) has been a major bottleneck in CMP systems. Using high-density memories inExpand
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Adaptive Prefetching Scheme Using Web Log Mining in Cluster-Based Web Systems
The main memory management has been a critical issue to provide high performance in web cluster systems.To overcome the speed gap between processors and disks,many prefetch schemes have been proposedExpand
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Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems
Multiprocessor systems have been popular for their high performance not only for server markets but also for computing environments for general users. With the increased software complexity,Expand
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Scalable and Efficient Bounds Checking for Large-Scale CMP Environments
We attempt to provide an architectural support for fast and efficient bounds checking for multithread work-loads in chip-multiprocessor (CMP) environments. Bounds information sharing and smartExpand
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A session key caching and prefetching scheme for secure communication in cluster systems
With the widespread use of cluster systems and ever increasing threat to computer security, it becomes more necessary to design and build secure cluster systems. Most cluster systems rely on securityExpand