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This paper presents the methods to reduce dynamic power consumption of a digital Finite Imppulse Respanse (FIR) filter these mrthods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear pheas architecture and applied to fir filters to power consumption reduced thus(More)
—In this paper an efficient high-speed architecture of Gaussian normal basis multiplier over binary finite field GF(2 m) is presented. The structure is constructed by using regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. Since the exponents are powers of 2, the(More)
This paper presents a high-speed and pipelined bit-parallel multiplier over binary finite fields for elliptic curve cryptosystems. The architecture of this multiplier is based on a parallel structure and multiplication by 2, so that the two inputs apply to the circuit simultaneously and in parallel form. Furthermore, the structure of the proposed circuit is(More)
In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using AND, XOR and XOR tree components. To have a low-cost implementation with low number of transistors, the block of AND gates are implemented by using NAND gates(More)