Bahram Rashidi

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This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow(More)
This paper presents a high-speed and pipelined bit-parallel multiplier over binary finite fields for elliptic curve cryptosystems. The architecture of this multiplier is based on a parallel structure and multiplication by 2, so that the two inputs apply to the circuit simultaneously and in parallel form. Furthermore, the structure of the proposed circuit is(More)
In this paper an efficient high-speed architecture of Gaussian normal basis multiplier over binary finite field GF(2) is presented. The structure is constructed by using regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. Since the exponents are powers of 2, the(More)
This paper focuses on the design of a low power and high performance FPGA based Digital Space Vector Pulse Width Modulation (DSVPWM) controller for three phase voltage source inverter. A new method is proposed to realize easy, accurate and high performance DSVPWM technique based on FPGA with low resource consumption and reduced execution time than(More)
This paper presents the methods to reduce dynamic power consumption of a digital Finite Imppulse Respanse (FIR) filter these mrthods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear pheas architecture and applied to fir filters to power consumption reduced thus(More)
This paper presents, a high speed FPGA implementation of fully digital controller for threephase Z-Source Inverter (ZSI) with two switching strategies include simple boost control and maximum boost control. In this method total of blocks are based on proposed digital circu its only with combinational logic and using pipelining technique. Since it is vital(More)
In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using AND, XOR and XOR tree components. To have a low-cost implementation with low number of transistors, the block of AND gates are implemented by using NAND gates(More)