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A practically viable multi-biometric recognition system should not only be stable, robust and accurate but should also adhere to real-time processing speed and memory constraints. This study proposes… (More)
A new low latency most significant bit first (MSBF), hybrid multiplier architecture is presented in this paper. This multiplier architecture requires fewer pipelining latches than the existing… (More)
A novel low latency, most significant digit-first, signed digit multiplier architecture is presented. The design of the multiplier is based on a new 2 bit adder cell. Judicious deployment of latches… (More)
A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes… (More)