Baback A. Izadi

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—In this paper, we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with ð k j Þ n spare nodes. Each set of j n regular nodes is connected to a spare node and the spare nodes are interconnected as either a ð k j Þ-ary n-cube if j 6 ¼ k 2 or a hypercube of(More)
Battery lifetime extension is a primary design objective for portable systems. This paper investigates how non-ideal properties of a battery impacts its lifespan. More specifically the paper analyzes experimental discharge characteristics of Alkaline, Nickel Cadmium, Nickel Metal Hydride and Lithium Ion batteries for both continuous and intermittent(More)
In this paper, we present a strongly fault-tolerant design for the l-level k-ary tree multiproces-sor and examine its reconfigurability. Our design assigns one spare node to the regular nodes of each sub-tree with l c levels. Moreover, spare nodes are interconnected to form a spare tree. Our approach utilizes the circuit-switched capabilities of the(More)
We present a real-time fault-tolerant design for an l-level k-ary tree multiprocessor and examine its reconfigurability. The k-ary tree is augmented by spare nodes and spare links. By utilizing the capabilities of wave-switching communication modules of the spare nodes, faulty nodes and faulty links can be tolerated. We consider two modes of operations. In(More)
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in(More)
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that controls DRAM modules in coarse grain in which the scheduler assigns appropriate power modes to memory banks at context switching time. The method controls the transition of(More)
This paper examines the errors committed by human operators of large networks and systems. It proposes a formal procedure in which system defense mechanisms are used to improve the coordination between human operators and computer agents. Further, it discusses and compares the effectiveness of different types of system defense mechanisms by performing(More)
In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using our method. The final solution gives a good(More)