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Journals and Conferences
This paper describes how simulation tools can be used in both optimising circuit performance and also in predicting parasitic capacitances associated with back end processing of silicon CMOS devices.… (More)
Graded n+ junctions, produced by implantation of arsenic and phosphorus, offer a simple but effective means of reducing electric fields in small geometry nMOSFET's, so suppressing hot-carrier… (More)