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The design of sigma-delta modulation analog-to-digital converters
TLDR
The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation. Expand
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A Two's Complement Parallel Array Multiplication Algorithm
  • C. Baugh, B. Wooley
  • Mathematics, Computer Science
  • IEEE Transactions on Computers
  • 1 December 1973
TLDR
An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. Expand
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Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
TLDR
An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Expand
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A 2.5-V sigma-delta modulator for broadband communications applications
TLDR
Oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. Expand
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Design techniques for high-speed, high-resolution comparators
TLDR
Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Expand
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1 A 1 . 8V Digital-Audio Sigma-Delta Modulator in 0 . 8-μ m CMOS *
Oversampling techniques based on sigma-delta ( Σ∆) modulation offer numerous advantages for the r ealization of high-resolution analog-to-digital (A/D) converters in a low-voltage envir onment. ThisExpand
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A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems
TLDR
A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. Expand
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The Design of Low-Voltage, Low-Power Sigma-Delta Modulators
1. Introduction. 2. Trends Toward Low-Voltage Power Supplies. 3. Analog-to-Digital Conversion. 4. Power Dissipation in Sigma-Delta A/D Converters. 5. Design of a Low-Voltage, High-ResolutionExpand
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A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling
TLDR
GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. Expand
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A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
TLDR
This paper introduces a continuous calibration technique for pipelined and successive approximation ADCs that avoids some of the limitations of earlier designs by performing the calibration in the analog domain. Expand
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