B. Sarkar

Publications105
h-index14
Citations690
Highly Influential Citations16
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Ring oscillators: Characteristics and applications
The structure and operating principle of ring oscillators (RO) have been described. The expression for the frequency of oscillation of a complementary metal oxide semiconductor (CMOS) delay cell…
Design and analysis of a first order time-delayed chaotic system
TLDR
The design and analysis of a new time-delayed chaotic system and its electronic circuit implementation and it is shown that, for some suitably chosen system parameters, the system shows hyperchaos even for a small or moderate delay.
Chaotic electronic oscillator from single amplifier biquad
Chaos and bifurcation in a third-order digital phase-locked loop
Design of Chaotic and Hyperchaotic Time-Delayed Electronic Circuit
The present paper reports a first order nonlinear retarded type time-delayed chaotic and hyperchaotic electronic circuit. The proposed circuit has three distinct advantages over the existing…
Characteristics of a variable length ring oscillator and its use in PLL based systems
This paper describes the properties of a multiplexer based variable length ring oscillator and the effects of using it as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) based…
Theory and performance of an electrically controlled microwave phase shifter
A microwave phase shifter (MPS) using a dc bias-controlled injection synchronized Gunn oscillator (ISGO) has been proposed. A continuous phase variation of a microwave frequency signal over a range…
On the dynamics of a periodic Colpitts oscillator forced by periodic and chaotic signals
Phase detector for data-clock recovery circuit
TLDR
A new type of phase detector which can be used in data-clock recovery circuits is reported which is free from data dependent jitter, which is the main problem with the Hogge phase detector.
Symmetric lock-range multilevel quantized digital phase locked FM demodulator
TLDR
A dynamic modification algorithm of the conventional digital phase-locked loop (CDPLL) design parameters is proposed to get a modified DPLL which has nearly symmetric two-sided acquisition range and better FM demodulation capability.
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