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Analog and mixed-signal benchmark circuits-first release
TLDR
A set of typical circuits described by netlists in HSPICE format is presented, which will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. Expand
The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects
TLDR
Techniques for the design of VLSI architectures for direct digital frequency synthesis have been introduced that allow for the optimization of the spurious response in the presence of finite-wordlength effects and these techniques have been applied to design a 14-bit-output DDFS. Expand
A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS
TLDR
A self-calibrated pipelined A/D converter technique potentially appropriate for high-resolution video applications that requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Expand
A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator
A 0.18/spl mu/m CMOS Bluetooth IC consumes 33mA in RX mode and 25mA in TX mode. The IC has a DLL-based GFSK demodulator with frequency offset cancellation. The receiver has -78dBm sensitivity at 0.1%Expand
Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS
TLDR
This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity, implemented in cost-effective 0.18µm RF CMOS technology. Expand
A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate ofExpand
A single-chip quad-band GSM/GPRS transceiver in 0.18 /spl mu/m standard CMOS
A 0.18 /spl mu/m CMOS single-chip fully integrated quad-band GSM/GPRS transceiver is presented. The low-IF receive section achieves -110dBm sensitivity at the antenna and -15dBm IIP3. TheExpand
A 30 MHz high-speed analog/digital PLL in 2 mu m CMOS
An analog/digital approach to data clock recovery that allows the implementation of a quasi-digital phase-locked loop (PLL) with an effective local clock frequency of 1 GHz in 2- mu m CMOS isExpand
Correction to "A Third-Order Modulator in 0.18- m CMOS With Calibrated Mixed-Mode Integrators"
TLDR
A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration with Digital BackgroundCalibration . Expand
A 13 bit 2.5 MHz self-calibrated pipelined A/D converter in 3 μm CMOS
A self-calibrated pipelined A/D (analog-to-digital) converter technique potentially applicable in high-resolution video applications is described. This approach potentially requires much less areaExpand
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