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A Fast Linear-Arithmetic Solver for DPLL(T)
A new Simplex-based linear arithmetic solver that can be integrated efficiently in the DPLL(T) framework by enabling fast backtracking, supporting a priori simplification to reduce the problem size, and providing an efficient form of theory propagation.
The YICES SMT Solver
Yices is an efficient SMT solver developed at SRI International that supports a rich combination of first-order theories that occur frequently in software and hardware modeling: arithmetic, uninterpreted functions, bit vectors, arrays, recursive datatypes, and more.
- B. Dutertre
- Computer ScienceCAV
- 18 July 2014
The latest release of Yices is described, namely, Yices 2.2.0, which presents the tool's architecture and discusses the algorithms it implements, and describes recent developments such as support for the SMT-LIBa 2.0 notation and various performance improvements.
Lightweight Key Management in Wireless Sensor Networks by Leveraging Initial Trust
Using initial trust built from a small set of shared keys, low-cost protocols enable neighboring sensors to authenticate and establish secure local links and are applied to secure a perimeter monitoring application.
Integrating Simplex with DPLL(T )
A new Simplex-based linear arithmetic solver that can be integrated efficiently in the DPLL(T ) framework and is even competitive with state-of-the-art tools specialized for the difference logic fragment is presented.
A Tutorial on Satisfiability Modulo Theories
This tutorial presentation is primarily directed at those who wish to build satisfiability solvers or to use existing solvers more effectively.
Using Model-based Intrusion Detection for SCADA Networks
It is believed that model-based monitoring, which has the potential for detecting unknown attacks, is more feasible for control networks than for general enterprise networks.
Modeling and Verification of a Fault-Tolerant Real-Time Startup Protocol Using Calendar Automata
A new modeling framework based on event calendars enables dense timed systems to be described without relying on continuously varying clocks and is applied to the fault-tolerant real-time startup protocol used in the Timed Triggered Architecture.
- Dejan Jovanovic, B. Dutertre
- Computer ScienceFormal Methods in Computer-Aided Design (FMCAD)
- 3 October 2016
This work presents a reformulation of IC3 that separates reachability checking from induction reasoning, and calls this new method property-directed k-induction (PD-KIND), which is shown to be more powerful than regular induction.