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Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
TLDR
The lifting scheme reduces the computational complexity of the discrete wavelet transform by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. Expand
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A Compact and Accurate Gaussian Variate Generator
TLDR
A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. Expand
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Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors
TLDR
Approximate computing has been considered to improve the accuracy-performance tradeoff in error-tolerant applications. Expand
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An investigation into crosstalk noise in DRAM structures
TLDR
The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. Expand
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Hardware Implementation of Nakagami and Weibull Variate Generators
TLDR
An efficient implementation of Nakagami- m and Weibull variate generators on a single field-programmable gate array (FPGA) is presented. Expand
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Modeling and Hardware Implementation Aspects of Fading Channel Simulators
TLDR
We present a fast and area-efficient FPGA implementation of a filter-based fading channel simulator on a single field-programmable gate array (FPGA) device. Expand
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A Single FPGA Filter-Based Multipath Fading Emulator
TLDR
We present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporally-correlated fading variates for emulating multipath fading radio channels. Expand
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A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes
TLDR
We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. Expand
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A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy
TLDR
This paper presents a novel method to approximate log2N that, unlike the existing approaches, rounds N to its nearest power of two. Expand
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Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders
TLDR
A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding and decoding. Expand
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