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Charge Collection and Charge Sharing in a 130 nm CMOS Technology
Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hitExpand
Layout Technique for Single-Event Transient Mitigation via Pulse Quenching
A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive areaExpand
Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits
Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS hasExpand
RHBD techniques for mitigating effects of single-event hits using guard-gates
Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hitsExpand
A Hardened-by-Design Technique for RF Digital Phase-Locked Loops
A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistantExpand
High-speed light Modulation in avalanche breakdown mode for Si diodes
The light emission process from a p-n junction in the forward-bias region is slow to respond to modulation signals due to the indirect band structure of silicon. Experimental results for aExpand
Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect
Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI), triple well,Expand
Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies
The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event crossExpand
Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology
Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nmExpand
Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic
Alpha particles incident on CMOS integrated circuits deposit charges on circuit nodes resulting in single-event transients (SETs). These transient errors propagate through the circuit and reach aExpand