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A unified algorithm for finding maximum and minimum object enclosing rectangles and cuboids
Abstract Given a set of n points in R 2 bounded within a rectangular floor F, and a rectangular plate P of specified size, we consider the following two problems: find an isothetic position of P suchExpand
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Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
TLDR
The recent emergence of lab-on-a-chip (LoC) technology has led to a paradigm shift in many healthcare-related application areas, e.g., point-of-care clinical diagnostics, high-throughput sequencing, and proteomics. Expand
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Fast Polygonal Approximation of Digital Curves Using Relaxed Straightness Properties
TLDR
In this paper, a new concept of approximate straightness is introduced by relaxing certain conditions of DSS, and an algorithm is described to extract segments from a digital curve. Expand
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CryptoScan: A Secured Scan Chain Architecture
TLDR
Scan based testing is a powerful and popular test technique. Expand
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Construction of isothetic covers of a digital object: A combinatorial approach
TLDR
An isothetic cover of a digital object not only specifies a simple representation of the object but also provides an approximate information about its structural content and geometric characteristics. Expand
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Number-theoretic interpretation and construction of a digital circle
TLDR
This paper presents a new interpretation of a digital circle in terms of the distribution of square numbers in discrete intervals. Expand
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Channel routing in Manhattan-diagonal model
  • S. Das, B. Bhattacharya
  • Engineering, Computer Science
  • Proceedings of 9th International Conference on…
  • 3 January 1996
TLDR
This paper presents a new technique of channel routing based on the Manhattan-Diagonal (MD) model that can route general channels with cyclic vertical constraints using w tracks, in O(l,w) time allowing overlapping of wiring segments in two layers. Expand
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Design of an optimal test pattern generator for built-in self testing of path delay faults
TLDR
A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. Expand
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Synthesis of online testable reversible circuit
TLDR
This article presents a technique for online fault detection under single missing-gate fault (SMGF) model in reversible circuits. Expand
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Permutation routing in optical MIN with minimum number of stages
TLDR
In this paper, it is shown that the routing delay and path-dependent loss in a fixed-stage N × N MIN, can be significantly reduced on the average by using a variable-stage shuffle-exchange network instead. Expand
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