• Publications
  • Influence
A replica technique for wordline and sense control in low-power SRAM's
TLDR
We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power of low-power SRAM's. Expand
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Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding
TLDR
We propose a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. Expand
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Low-power SRAM design using half-swing pulse-mode techniques
TLDR
This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. Expand
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Fast low-power decoders for RAMs
TLDR
We analyze the problem of optimally sizing the decoder chain with RC interconnect and find the optimum fan-out to be about 4, just as in the case of a simple buffer chain. Expand
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Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor
TLDR
A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. Expand
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An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology
TLDR
We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal-oxide-semiconductor (CMOS) technology. Expand
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Adaptive Pulse Width Control and Sampling for Low Power Pulse Oximetry
  • S. Gubbi, B. Amrutur
  • Engineering, Medicine
  • IEEE Transactions on Biomedical Circuits and…
  • 1 April 2015
TLDR
This paper presents a power optimized photoplethysmographic sensor interface to sense arterial oxygen saturation, a technique to dynamically trade off SNR for power during sensor operation, and a simple algorithm to choose when to acquire samples in photopletherysmography. Expand
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Techniques to reduce power in fast wide memories [CMOS SRAMs]
Memories contain large arrays with high capacitance bitlines and IO lines. To reduce the power of memory accesses we limit the swings on these by controlling the time the lines are driven by using aExpand
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A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read
TLDR
In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. Expand
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Applications of on-chip samplers for test and measurement of integrated circuits
TLDR
We present a simple sampling technique to display the analog waveforms of high bandwidth on-chip signals on a laboratory oscilloscope. Expand
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