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A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. V<sub>t</sub> tuning is found to be proportional to the net dipole(More)
If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering,(More)
This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in(More)
We show for the first time that control of the crystalline phases of HfO<sub>2</sub> by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the(More)
We describe an NMOS band edge solution that uses a metal gate doped with Lanthanide elements to achieve work functions as low as 4.05eV. The capping interlayers used in previous works are no longer necessary, and metal gate implementation became much simpler. Using this electrode, low V<sub>th</sub> value and high mobility suitable for high performance(More)
The effective work function (EWF) of ternary metal-aluminum-nitride (M-Al-N, M=Ta, Ti, Mo, W) metal gate electrodes in high-k dielectric gate stacks has been investigated. With the addition of Al, the EWF can be tuned toward p-type (~5 eV) by 250 meV compared to the EWF of the binary metal nitride. Low threshold voltage (V<sub>t</sub>) of ~ -0.35 V, an(More)
A dry etch process for metal/high-k stacks has been developed to solve the integration problems associated with wet etch removal of high-k dielectric from the source and drain (S/D) areas. An in-situ plasma (O<sub>2</sub>) treatment has been introduced for the first time to cure the damage induced by the high-k dry etch process. Excellent electrical(More)
A metal/high-k gate stack with P-type band edge effective work function (EWF) of 5.1-5.2 eV is achieved through optimization of a Ru-Al based metal electrode. The critical factors controlling the high EWF values are found to be Al incorporation at the high-k/SiO<sub>2</sub> interface and stabilization of the conductive RuO<sub>2</sub> layer at the(More)
In this work, a plasma etch technique for removing high-k dielectric from the source and drain (S/D) areas after metal/high-k gate stack patterning has been developed. To cure the plasma damage induced during the plasma etch of high-k films, an in situ plasma treatment with O<sub>2</sub> or N<sub>2</sub> was applied to several high-k compositions. This(More)
Effects of TiN thickness on metal/high-k SOI FinFET characteristics were studied. Compared to planar SOI devices, our metal/high-k FinFETs showed improved carrier mobility due to a vertical strain effect. Almost 2times higher field mobility for a (110)/lang110rang nMOSFET was achieved. With increasing TiN thickness, electron and hole mobility improved in(More)
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