B. Premalatha

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
In this paper, Master Slave Match Line (MSML) design is adopted in conventional Content addressable memory (CAM) cell. The main objective of this design is to achieve Low power and high speed. MSML consists of two Master Match Line (MML) and two Slave Match Line (SML). The Circuit was implemented using Microwind tool in 45nm technology. Performance metrics(More)
The Parallel Self Timed adder (PASTA) is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits and do not need any of the carry chain propagation. The main objective of this paper is to reduce the power consumption and also to increase the performance. The existing design attains good performance(More)
  • 1