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In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um<sup>2</sup> SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM)(More)
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