B. Bornoosh

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In this paper a new architecture for reducing the phase noise of digital carrier recovery (CR) algorithms is proposed. This architecture is useful for high-order QAM modulations in which very fine phase noise characteristic is needed for RF oscillators and for IF digital down converters (DDC). Using software aided algorithm, this architecture can be(More)
This paper presents the design of a dynamic reconfigurable processor using an array of two dimensional logarithmic numbering system (LNS) processing elements and registers. By programming the processor, the array configures dynamically during operation and executes the required task with different structures in each phase. The proposed coarse grain array(More)
Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors or to reduce the signal to noise ratio requirement in transmission process. This paper presents an area-efficient 8-error correcting RS (255,239) decoder architecture using RiBM algorithm, implemented on a 0.25-¿m CMOS technology with a(More)
In this paper, a new technique for the OFDM timing synchronization problem under the multi-path channel conditions is presented. The algorithm exploits a pseudo-noise sequence instead of the duplicated version of OFDM frame tail as the guard interval. Different techniques are used to reduce the potential ISI caused by this operation. To evaluate the(More)
In this paper, a reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The modulator consists of two sub-blocks and has a single bit output which makes it best for this application. A good shaping of quantization noise is achieved using a new architecture for a digital third-order delta-sigma(More)
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