Aznam Yacoub

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Verification and Validation (V&V) of Systems is an important process in the development of systems, in order to ensure that they are reliable and operational. Among methods of V&V, there are two that seem to be opposite to each other: simulation, which is empirical, and formal verification, which is comprehensive. Moreover, simulation and formal(More)
Discrete Event system Specification (DEVS) is a simple comprehensive way to describe complex discrete-event systems in a hierarchical way. Few years ago, Finite and Deterministic DEVS (FDDEVS) was introduced to support verification analysis of a subclass of DEVS problems, in the same way as formal methods. This paper presents guidelines to transform(More)
Efficient modelling and verification of models need an accurate representation of systems. Especially, PROMELA cannot represent time as quantitative properties. That means some properties depending on time cannot be checked with SPIN model-checker. Discrete-Time approaches and dense representation of time were successfully introduced in SPIN as extensions(More)
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